Semtech ACS8526
LC/P Lite Line Card Protection Switch for PDH, SONET, or SDH Systems
- Has fast activity monitors on the inputs, and raises a flag on a pin upon loss of activity on the selected input
- Protection switching between input reference clock sources is controlled by an external pin
- Has two SEC reference clock input ports, configured for expected frequency by setting hardware pins or by writing to registers via the serial interface
- Can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards
- Generates two independent SEC clock outputs, one on a PECL/LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins, or by writing to registers via the serial interface
- Hardware selectable spot frequencies range from 1.544 MHz up to 155.52 MHz, with further options for N x E1/DS1 and 311.04 MHz via register selection
- Provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output, both with programmable pulse width and polarity
- Advanced configuration possibilities are available via the SPI-compatible serial port, however the basic configuration of I/O frequencies and SONET/SDH selection by hardware make the device suitable for standalone operation, i.e., no need for a microprocessor.
Features
- Line card protection switch - partners Semtech SETS devices for Stratum 3E/3/4E/4 PDH, SONET/SDH applications
- High performance DPLL/APLL solution
- Output jitter compliant to STM-1
- Two independent SEC inputs ports (TTL)
- Four independent output ports: .ul
- Two clock ports: one PECL/LVDS, one TTL
- Two Syncs (TTL): 8 kHz FrSync & 2 kHz MFrSync./ul
- TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz
- PECL/LVDS port: spot frequencies 2 kHz to 311 MHz
- N x E1/DS1 mode
- Programmable pulse width and polarity on Syncs
- SONET/SDH frequency translation
- Digital Holdover mode on input failure
- Separate activity monitors and register alarms on each input
- "Loss of activity" on selected input flagged on dedicated pin
- Source switch under external hardware control
- PLL "Locked" and "Acquisition" bandwidth selectable from 18, 35 or 70 Hz
- Configurable via serial interface or hardware pins
- Output clock phase continuity to GR-1244-CORE
- Single 3.3 V operation, 5 V I/O compatible
- IEEE 1149.1 JTAG Boundary Scan is supported
- Operating temperature (ambient) of -40 to +85 °C
- Available in 64-pin LQFP package
Order Codes
- ACS8526 : NCNR, 160 per tray, ok to order partial tray quantities
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